Lab3_manual_UG_GR

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University of Texas, Rio Grande Valley *

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429

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Electrical Engineering

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Apr 3, 2024

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pdf

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ECEN 428/722 – Lab 3: Folded and Unfolded IIR Filter Design on FPGA Texas A & M University Page 1 1 Introduction In this lab, we will extend our IIR design done in the previous lab. We will implement unfolded and folded IIR filter designs and compare their differences. For this lab, you are expected to complete the following tasks: a) Implement the unfolded IIR filter design. b) Implement the folded IIR filter design. c) Summarize the differences in the implementation between unfolding and folding filter design. 1.1 Introduction to Unfolding and Folding Unfolding is a transformation technique that increases the throughput of a digital signal processing program by duplicating the functional blocks while maintaining functionality. On the other hand, folding converts multiple operations into a single operation block and minimizes the number of functional blocks needed in synthesizing the digital signal processing system. Please refer to the lectures (or chapters 5 and 6 from the text authored by Keshab Parhi prescribed in the syllabus) to understand the unfolding and folding algorithms before the lab. We need to design IIR for this lab based on the same IIR design. Figure 1, Figure 2, and Figure 3 show the original, unfolded, and folded design of the IIR filter, respectively. Figure 1: IIR Original Design

ECEN 428/722 – Lab 3: Folded and Unfolded IIR Filter Design on FPGA Texas A & M University Page 2 Figure 2: IIR Unfolded Design Figure 3: IIR Folded Design 2 Lab Design of Unfolded IIR Now we start to implement the designs. a) If using Olympus server, transfer the base_vivado.zip file form personal computer to Olympus using the scp command (instructions shown in Lab1). b) Log into Olympus. Unzip the zip file. Rename the extracted directory from base_vivado to lab3_vivado c) Source the 2023 version of Vivado and Vitis: source /opt/coe/Xilinx/Vitis/2023.1/settings64.sh source /opt/coe/Xilinx/Vivado/2023.1/settings64.sh d) Start Vivado, then open the project base.xpr under lab3_vivado/base

ECEN 428/722 – Lab 3: Folded and Unfolded IIR Filter Design on FPGA Texas A & M University Page 3 e) Click on File à Add Sources . Select Add or create design sources . Click Add Files and choose the files IIR_unfold.v , multiply.v from the lab3_codes folder. Finally and click finish . Refer to figure. f) In the same manner, also add the testbench for the design. Click on File à Add Sources . Select Add or create simulation sources . Choose the file IIR_unfold_tb.v and flick Finish. Refer to the figure below on how the design hierarchy should look after adding these files. g) Now its your job to complete the Verilog code for the 2-unfolded IIR module according to the unfolding algorithm taught in class. You will need to implement your code in the IIR_unfold.v file. Remember to use an 8-bit signed fixed-point number for calculation in the lab, with 4 bits for the fractional part, 3 bits for the interger part and 1 bit for sign. After you finish coding IIR_unfold.v , we can run behavioral simulation. Before simulation, please right click on IIR_unfold_tb and click Set as Top . Refer to figure below.

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