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Nt1310 Unit B Assignment

Satisfactory Essays

The second challenge is outlined in [3]. The described problem there is the bus connection between the cores and the L2 cache. It is necessary to organize the access from the cores on the cache with a bus arbitration protocol. In this case the Time Division Multiple Access (TDMA) protocol is used. This means that each core gets an exact time slot for the access. The assignment of the time slots is handled in round robin [3, p. 3]. Depending on the access time on the bus, the core will either immediately be granted to access the bus or must wait until his next time-slot. This happens if the pre-estimated access duration is longer than the remaining slot time. Based on these facts, [3] prepares an equation for the maximum delay: Dmax = ((nc 1)sl) + (z 1) …show more content…

Having a good estimation on the access duration will obviously lead to a much better performance of the program, because it determines if an access will be granted directly or not [3, p. 3]. Waiting for the next time slot of a core can consume a lot of time in multi-core chips. In this topic also timing anomalies exist and can complicate the WCET analysis [3, p. 9]. Thus it can occur that a cache hit will lead to the worst-case behavior instead of a cache miss. After presenting the challenges, the approaches for calculating the worst case execution time will be outlined. For each approach, there will be also given the outcomes and limitations that are made from the authors themselves. At first, the focus is on a better estimation of the behavior of the shared L2 caches in the next chapter. Afterwards, a solution for a better estimation of the access times on the bus will be

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