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Consider a system with 20 requests out of 20,4 requests are already in cache memory.what will be the hit ratio?
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- In a computer with a 32-bit data-bus, how many 4-bit wide memory components are used? the answer to this part is 32/4 = 8 components (2-bit wide) I need the answer to part two, please If the size of each 4-bit memory component is 4 x n cells where n = 1G (i.e., 4 x n uniquely addressable locations—n : row, 4 : 2 column/width), what is the total capacity of the memory system? Show your answer in power of 2. (hint: 1000 ~ 210)Suppose that in 1000 memory references there are 50 misses in the first-level cache, 20 misses in the second-level cache, and 5 misses in the third-level cache. Assume the miss penalty from the L3 cache to memory is 100 clock cycle, the hit time of the L3 cache is 10 clocks, the hit time of the L2 cache is 4 clocks, the hit time of L1 is 1 clock cycle. What is the average memory access time?For a system, RAM = 64KB, Block size = 4 bytes, Cache size = 128 bytes, Direct mapped cache.Calculate the Hit ratio while CPU runs program “Test_Cache”. Also count how many blocks arereplaced in cache memory assuming the cache is empty at the beginning.For the same RAM, block size and Cache memory, what would be the Hit ration in case of FullyAssociative Mapping?For the same RAM, block size and Cache memory, what would be the Hit ration in case of 4-way SetAssociative Mapping?Main Program—“Test_Cache”
- An university student was trying improve the performance of one of the test computers. Computer initially had 2-way set associative mapping with 16kb cache and 128 KB byte addressable main memory with 256 bytes block size. It was later decided to change it to 4-way cache. Will there be an increase or decrease in tag directory size due to this change? By how much?.In a computer with a 32-bit data-bus, how many 4-bit wide memory components are used? the answer to this part is 32/4 = 8 components (2-bit wide) I need the answer to part two, please If the size of each 4-bit memory component is 4 x n cells where n = 1G (i.e., 4 x n uniquely addressable locations-n: row, 4:2 column/width), what is the total capacity of the memory system? Show your answer in power of 2. (hint: 1000 ~ 210)A computer uses virtual memory, and a new solid-state drive (SSD) as space for paging. Refer to the last ppt file. In the case presented there, the hard disk drive (HDD) required 25 ms to read in a page, and a rate of 1 page fault per 1000 references introduced a 250 slowdown. If the SSD offers a time of only 80 µs, what is the slowdown in performance caused by 1 pf per 1000 references (you are not concerned with dirty vs. clean pages). What is the maximum rate of page faults you can accept if you want no more than a 5% slowdown in execution using virtual memory? Know your metric prefixes and symbols for time: s for seconds, ms for milliseconds, µs for microseconds, ns for nanoseconds.
- Take into account the following scenario: we have a byte-addressable computer with 2-way set associative mapping, 16-bit main memory addresses, and 32 blocks of cache memory. Since there are 8 bytes in a block, you can use that information to calculate how big the offset field has to be.Consider a fully-associative cache of size 4. Each slot in the cache can have just one item (i.e. the line size is 1 item). The cache is empty to start with. The cache uses an LRU replacement policy: every slot has a counter; every time a slot is accessed, a global counter is incremented and the value is stored in the slot counter; the slot with the lowest counter value is chosen for replacement. Sequence Id 1 2 3 4 5 6 7 8 10 Address Ox0012 0x0014 Ox0016 Ox0018 0x0016 0x0012 0x0020 Ox0022 0x0014 Ox0012 Hit/Miss Accesses 1 to 10 are respectively: Select one: O a. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Miss, Miss O b. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Hit, Hit O. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Hit, Miss O d. Miss, Miss, Miss, Miss, Hit, Miss, Miss, Miss, Miss, Hit O e. Miss, Miss, Miss, Miss, Hit, Hit, Miss, Miss, Miss, HitA 2-way set associative cache consists of four sets. Main memory contains 2K blocks of eight words each. Show the main memory address format that allows us to map addresses from main memory to cache. Be sure to include the fields as well as their sizes. Compute the hit ratio for a program that loops 6 times from locations 8 to 51 in main memory. You may leave the hit ratio in terms of a fraction. Please show details how you obtain the result.
- Discuss the First-Come, First-Served (FCFS) disk scheduling algorithm. Please explain this algorithm using your own words in such a way that everyone with some understanding of computers and computer programming will understand it.Then provide an example of application of your algorithm for a disk queue with 8 requests (e.g.: 98, 18, 370, 122, 14, 12, 6, 67). Choose your own disk queue with 8 requests. Compute the total head movement for your example. Describe the computation process in detail, don't just list the final result.If memory read cycle takes 100 ns and a cache read cycle takes 20 ns, then for four continuous references, the first one brings the main memory contents to cache and the next three from cache. Find the time taken for the Read cycle with and without Cache? What is the Percentage speedup obtained?Question 18 Suppose we have a byte-addressable computer using 2-way set associative mapping with 16-bit main memory addresses and 32 blocks of cache. Suppose also that each block contains 8 bytes. The size of the block offset field is bits, the bits. size of the set field is bits, and the size of the tag hield is