A direct-mapped cache consists of 8 blocks. A byte-addressable main memory contains 4K blocks of eight bytes each. Access time for the cache is 20 ns and the time required to fill a cache slot from main memory is 300 ns. Assume a request is always started in sequential to cache and then to main memory. If a block is missing from cache, the entire block is brought into the cache and the access is restarted. Initially, the cache is empty. c) Compute the effective access time for this program. Show me how to solve using this equation: EAT = H x AccessC + (1 – H) x AccessMM where H is the cache hit rate and AccessC and AccessMM are the access times for cache and main memory, respectively. thanks

A direct-mapped cache consists of 8 blocks. A byte-addressable main memory contains 4K blocks of eight bytes each. Access time for the cache is 20 ns and the time required to fill a cache slot from main memory is 300 ns. Assume a request is always started in sequential to cache and then to main memory. If a block is missing from cache, the entire block is brought into the cache and the access is restarted. Initially, the cache is empty. c) Compute the effective access time for this program. Show me how to solve using this equation: EAT = H x AccessC + (1 – H) x AccessMM where H is the cache hit rate and AccessC and AccessMM are the access times for cache and main memory, respectively. thanks

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter11: Operating Systems

Section: Chapter Questions

Problem 22VE

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A direct-mapped cache consists of 16 blocks. A byte-addressable main memory contains 4K blocks of 16 bytes each. Access time for the cache is 30 ns and the time required to fill a cache slot from main memory is 250 ns. Assume a request is always started in sequential to cache and then to main memory. If a block is missing from cache, the entire block is brought into the cache and the access is restarted. Initially, the cache is empty. a) Show the main memory address format that allows us to map addresses from main memory to cache. Be sure to include the fields as well as their sizes. b) Compute the hit ratio for a program that loops 4 times from locations 0 to 42 (base 10) in memory. c) Compute the effective access time for this program.
A request that cannot be satisfied in the cache is issued by the processor while the write buffer returns a block to main memory. What should happen in this case?
In the event that a request cannot be fulfilled by the cache, the processor will submit a request to main memory while the write buffer delivers the relevant data block. What steps need to be taken here?
A computer of 32 bits has a cache memory of 64 KB with a cache line size of 64 bytes. The cache access time is 20 ns, and the miss penalty is 120 ns. The cache is 2-way associative. a) What is the number of cache lines? b) What is the number of cache sets? c) What is the number of lines per set? d) Draw a scheme of this cache. e) Calculate the time to read a word in case of miss.
Q4) A computer has an 8 GByte memory with 64 bit word sizes. Each block of memory stores 16 words. The computer has a direct-mapped cache of 128 blocks. The computer uses word level addressing. What is the address format? If we change the cache to a 4- way set associative cache, what is the new address format?
When a block leaves the write buffer and returns to main memory, does anything need to happen if the processing unit makes a cache-unfulfilled request?
When a block is being returned from the write buffer to main memory, what should the CPU do if a cache request arrives at the same time?
When a cache request comes in while a block is being sent back to main memory from the write buffer, what should the CPU do?
This function will be able to look at which fields in a log entry that it needs to. When you use 64-byte cache blocks and don't prefetch, the following code calculates the average number of cache misses for each entry in the cache.
b. Cache memory systems are designed such that the computer first checks the L1 cache for the desired memory. If the data is there, it accesses it and is done. It only checks the L2 cache if the data is not found in the L1 cache. Likewise, the computer checks the L3 cache if the desired data is not found in the L2 cache, and finally it on only checks main memory if the data is not found in the L3 cache. Imagine a computer system with the following cache access times: L1 cache: 3 processor cycles L2 cache: 10 processor cycles L3 cache: 25 processor cycles Main memory: 100 processor cycles So, in the best case, the desired data-would be immediately found in the L1 cache, which requires only 3 cycles to check. Conversely, in the worst case, the desired data would only be in main memory, which would require 138 cycles to access (3 cycles to check L1 cache + 10 cycles to check L2 + 25 cycles to check L3 + 100 cycles to access main memory). What is important, however, is the average amount…
Q: A set-associative cache has a block size of 256 bytes and a set size of 2. The cache can accommodate 32 KB. . The size of main memory is 256 KB. Design the cache structure and show how the processor’s addresses are interpreted. Note: this question is related from coal subject.
Q: A set-associative cache has a block size of 256 bytes and a set size of 2. The cache can accommodate 32 KB. . The size of main memory is 256 KB. Design the cache structure and show how the processor’s addresses are interpreted.Note: this question is related from coal subject.