A system has 4-kB pages, a 48-bit virtual address space, and a 33-bit physical address space. Assuming that page tables contain only physical page numbers--that is, no meta-data--that it is implemented as a simple lookup table, and that physical page numbers are packed into the smallest number of 8-bit bytes that can hold them (there may be wasted bits at each entry), how many bytes of memory are required to hold the entire page table? Please enter your answer in bytes.
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- Consider an operating system that uses 48-bit virtual addresses and 16KB pages. The system uses a hierarchical page table design to store all the page table entries of a process, and each page table entry is 4 bytes in size. What is the total number of pages that are required to store the page table entries of a process, across all levels of the hierarchical page table?A computer system has the segmented paging for virtual memory. The memory is byte addressable. Both virtual and physical address spaces contain 216 bytes each. The virtual address space is divided into 8 non-overlapping equal size segments. The memory management unit has a hardware segment table, each entry of which contains the physical address of the page table for the segment. Page tables are stored in the main memory and consists of 2 byte page table entries What is the minimum page size in bytes so that the page table for a segment requires at most one page to store it and also give the division of virtual address ?In the S/370 architecture, a storage key is a control field associated with each page- sized frame of real memory. Two bits of that key that are relevant for page replace- ment are the reference bit and the change bit. The reference bit is set to 1 when any address within the frame is accessed for read or write, and is set to 0 when a new page is loaded into the frame. The change bit is set to 1 when a write operation is per- formed on any location within the frame. Suggest an approach for determining which page frames are least-recently-used, making use of only the reference bit.
- Consider a byte-addressable computer with 32-bit addresses, a cache capable of storing a total of 64K bytes of data, and cache blocks of size 128 bytes. If the computer uses direct mapping, the format of the memory address is as follows: bits for the tag field, bits for the cache block number, and bits for the block offset.Suppose a computer using fully associative cache has 220220 words of main memory and a cache of 128 blocks, where each cache block contains 16 words. (a) How many blocks of main memory are there? (b) What is the format of a memory address as seen by the cache, that is, what are the sizes of the tag and word fields? (c) To which cache block will the memory reference 01D872_{16}01D872_{16} map?In a certain computer, the virtual addresses are 32 bits long and the physical addresses are 48 bits long. The memory is word addressable. The page size is 16 kB and the word size is 2 bytes. The Translation Look-aside Buffer (TLB) in the address translation path has 64 valid entries. Hit ratio of TLB is 100% then maximum number of distinct virtual addresses that can be translated is K.
- Suppose a computer using set associative cache has 216 words of main memory and a cache of 128 blocks, and each cache block contains 8 words. If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields?Consider a computer system with a 30-bit logical address and 4-KB page size. The system supports up to 512 MB of physical memory. How many entries are there in each of the following? Assume that each page table entry is 4 Bytes. c. A conventional single-level page table?d. An inverted page table?e. A two-level hierarchical page table? Consider a virtual memory system with a 50-bit logical address and a 38-bit physical address. Suppose that the page/frame size is 16K bytes. Assume that each page table entry is 4 Bytes. a. How many frames are in the systems? How many pages in the virtual address space for a process? b. If a single-level page table is deployed, calculate the size of the page table for each process. c. Design a multilevel page table structure for this system to ensure that each page table can fit into one frame. How many levels do you need? Draw a figure to show your page systemsConsider an operating system that uses 48-bit virtual addresses and 16KB pages. The system uses a multi-level page table design to store all the page table entries of a process, and each page table entry and index entry are 4 bytes in size. What is the total number of page that are required to store the page table entries of a process, across all levels of the page table? You may follow the hint below or finish from scratch to fill the blanks. Please show your calculations to get partial points like 2^10/2^4=2^6. 1. We need to calculate the total number of page table entries needed for a process (i.e., the total number of pages for a process) 2. We need to calculate how many entries each page can store 3. With 1 and 2, we can calculate how many pages needed for the lowest (innermost) level 4. Each page from 3 requires an entry (pointer) in the upper (next) level. We need to calculate how many pages are required to store this next level entries (please note the entry size is always 4…
- Suppose a computer using fully associative cache has 4G bytes of byte-addressable main memory and a cache of 512 blocks, where each cache block contains 128 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag and offset fields? c) To which cache block will the memory address 0x018072 map?Suppose a byte-addressable computer using set associative cache has 2^24 bytes of main memory and a cache size of 64K bytes, and each cache block contains 32 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?3) Suppose we have a computer that uses a memory address word size of 8 bits. This computer has a 16- byte cache with 4 bytes per block. The computer accesses a number of memory locations throughout the course of running a program. Suppose this computer uses direct-mapped cache. The format of a memory address as seen by the cache is shown below: Tag 4 bits Block 2 bits Offset 2 bits The system accesses memory addresses in this exact order: 0x6E, 0xB9, 0x17, 0xE0, 0x4E, 0x4F, 0x50, 0x91, 0xA8, 0xA9, 0xAB, 0xAD, 0x93, and 0x94. Fill out the following tables: a) Address Hit Reference or Miss Comments b) Show the final contents of cache for direct addressing: Block Cache Contents Tag (represented by address)