A translation look-aside buffer is used to a. cache page table entries. b. store page size. c. size of the logical address space of the currently running process. d. store the address of the page table in memory.
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- What is Translation Look-Aside Buffer used in paging? answer a)It is a memory that is searched when a page is not found in page table b)It is part of the physical memory to hold process control blocks c)It is a bank of special registers inside the processor d)It is an associative memory that can do parallel frame search in hardwareIn the S/370 architecture, a storage key is a control field associated with each page- sized frame of real memory. Two bits of that key that are relevant for page replace- ment are the reference bit and the change bit. The reference bit is set to 1 when any address within the frame is accessed for read or write, and is set to 0 when a new page is loaded into the frame. The change bit is set to 1 when a write operation is per- formed on any location within the frame. Suggest an approach for determining which page frames are least-recently-used, making use of only the reference bit.Paging: Select all of the following statements that are true. Systems that use paging but do not support inverted page tables maintain at least one separate page table for each process. The frame table is a system-wide data structure. When paging is applied, the selected page size determines which part of a virtual address belongs to the page number and which to the offset. The page size may differ from the frame size. The Translation Look-aside Buffer (TLB) represents a page directory for all pages in the system. Paging is prone to internal fragmentation.
- Suppose a computer using direct mapped cache has 232 byte of byte-addressable main memory, and a cache of 1024 blocks, where each cache block contains 32 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag, block, and offset fields? c) To which cache block will the memory address 0x000063FA map?A digital computer has a memory unit of 64K X 16 and a cache memory of 1K words. The cache uses direct mapping with a block size of four words.i) How many bits are there in the tag, index, block and word fields of the address format?ii) How many bits are there in each word of cache, and how are they divided into functions? Include a valid bit.iii) How many blocks can the cache accommodate?Suppose a computer using fully associative cache has 220 words of main memory and a cache of 128 blocks, where each cache block contains 16 words. (a) How many blocks of main memory are there? (b) What is the format of a memory address as seen by the cache, that is, what are the sizes of the tag and word fields? (c) To which cache block will the memory reference 01D872_{16} map?
- Design a memory map to work with 8085 Microprocessor to have 8K byte ROM and 2K byte RAM. ROM should start from memory location 0000H and RAM immediately follows it. Use exhaustive decoding scheme?3. The series of memory address references given as word addresses are 122, 126, 126, 126, 116, 300, 116, and 118. Assume a direct-mapped cache with eight one-word blocks that is initially empty. Label each reference in the list as a hit or miss and show the contents of the cache with figure after each reference.A computer of 32 bits has a cache memory of 64 KB with a cache line size of 64 bytes. The cache access time is 20 ns, and the miss penalty is 120 ns. The cache is 2-way associative. a) What is the number of cache lines? b) What is the number of cache sets? c) What is the number of lines per set? d) Draw a scheme of this cache. e) Calculate the time to read a word in case of miss.
- Suppose a computer using direct mapped cache has 232 words of main memory, and a cache of 1024 blocks, where each cache block contains 32 words. How many blocks of main memory are there? What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag, block, and offset fields? To which cache block will the memory reference 0003101A16 map?Assume we have a page table when some pages aren’t in main memory. Is there any occurrence of page faults ? If not, please explain why. And if so, what exactly do you mean by “page fault” and how do you handle them? Explain with a diagramSuppose a computer using fully associative cache has 4G bytes of byte-addressable main memory and a cache of 512 blocks, where each cache block contains 128 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag and offset fields? c) To which cache block will the memory address 0x018072 map?