A typical digital signal processing (DSP) system is given in figure below. ADC has DOMHZ sampling clock and every samples will be captured by FPGA for backend processing. n interpolator increases the sampling rate by a factor of 4 to generate the sample stream of y(n). nen, a decimation block will reduce the sampling rate by a factor of 15 to generate sample ream of z(n). 100MHZ FPGA y(n) z(n) Decimator x(t) x(n) ADC Interpolator LPF1 LPF2 When LPF1 (Low Pass Filter 1) and LPF2 are implemented using a 30-taps FIR structure, and the system must operate in streaming way (every samples must be processed without any halt), what will be required FPGA clock frequency and what type of FIR filter structures should be used? Input samples are 12-bits and coefficients are 10-bits for both filters. Determine the number and the size of multiplication and addition operations in FPGA to implement LPF1 and LPF2. Comment on the bit growth and what kind of digital operations should be implemented before LPF2 to reduce the hardware cost?

Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
Section: Chapter Questions
Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...
icon
Related questions
Question
A typical digital signal processing (DSP) system is given in figure below. ADC has
100MHZ sampling clock and every samples will be captured by FPGA for backend processing.
An interpolator increases the sampling rate by a factor of 4 to generate the sample stream of y(n).
Then, a decimation block will reduce the sampling rate by a factor of 15 to generate sample
stream of z(n).
100MHZ
FPGA
У (n)
z(n)
Decimator
x(t)
x(n)
ADC
Interpolator
LPF1
LPF2
When LPF1 (Low Pass Filter 1) and LPF2 are implemented using a 30-taps FIR
structure, and the system must operate in streaming way (every samples must be processed
without any halt), what will be required FPGA clock frequency and what type of FIR filter
structures should be used? Input samples are 12-bits and coefficients are 10-bits for both
filters. Determine the number and the size of multiplication and addition operations in
FPGA to implement LPF1 and LPF2. Comment on the bit growth and what kind of digital
operations should be implemented before LPF2 to reduce the hardware cost?
Transcribed Image Text:A typical digital signal processing (DSP) system is given in figure below. ADC has 100MHZ sampling clock and every samples will be captured by FPGA for backend processing. An interpolator increases the sampling rate by a factor of 4 to generate the sample stream of y(n). Then, a decimation block will reduce the sampling rate by a factor of 15 to generate sample stream of z(n). 100MHZ FPGA У (n) z(n) Decimator x(t) x(n) ADC Interpolator LPF1 LPF2 When LPF1 (Low Pass Filter 1) and LPF2 are implemented using a 30-taps FIR structure, and the system must operate in streaming way (every samples must be processed without any halt), what will be required FPGA clock frequency and what type of FIR filter structures should be used? Input samples are 12-bits and coefficients are 10-bits for both filters. Determine the number and the size of multiplication and addition operations in FPGA to implement LPF1 and LPF2. Comment on the bit growth and what kind of digital operations should be implemented before LPF2 to reduce the hardware cost?
Expert Solution
steps

Step by step

Solved in 2 steps with 1 images

Blurred answer
Knowledge Booster
Nyquist Plot
Learn more about
Need a deep-dive on the concept behind this application? Look no further. Learn more about this topic, electrical-engineering and related others by exploring similar questions and additional content below.
Similar questions
  • SEE MORE QUESTIONS
Recommended textbooks for you
Introductory Circuit Analysis (13th Edition)
Introductory Circuit Analysis (13th Edition)
Electrical Engineering
ISBN:
9780133923605
Author:
Robert L. Boylestad
Publisher:
PEARSON
Delmar's Standard Textbook Of Electricity
Delmar's Standard Textbook Of Electricity
Electrical Engineering
ISBN:
9781337900348
Author:
Stephen L. Herman
Publisher:
Cengage Learning
Programmable Logic Controllers
Programmable Logic Controllers
Electrical Engineering
ISBN:
9780073373843
Author:
Frank D. Petruzella
Publisher:
McGraw-Hill Education
Fundamentals of Electric Circuits
Fundamentals of Electric Circuits
Electrical Engineering
ISBN:
9780078028229
Author:
Charles K Alexander, Matthew Sadiku
Publisher:
McGraw-Hill Education
Electric Circuits. (11th Edition)
Electric Circuits. (11th Edition)
Electrical Engineering
ISBN:
9780134746968
Author:
James W. Nilsson, Susan Riedel
Publisher:
PEARSON
Engineering Electromagnetics
Engineering Electromagnetics
Electrical Engineering
ISBN:
9780078028151
Author:
Hayt, William H. (william Hart), Jr, BUCK, John A.
Publisher:
Mcgraw-hill Education,