achine codes of the MIPS instructions (all the way to HEX values). Instruction 1: sub $s3, $t2, $v1 Instruction 2: sw $t3, -16($s1) a)Show all the bit fields of instruction 1 & 2. b)Type the machine
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Assemble the machine codes of the MIPS instructions (all the way to HEX values).
Instruction 1: sub $s3, $t2, $v1
Instruction 2: sw $t3, -16($s1)
a)Show all the bit fields of instruction 1 & 2.
b)Type the machine code of instruction 1&2 in HEX.
Step by step
Solved in 3 steps
- Convert the given hex value to its R-format MIPS instruction by completing the following table. The instruction and letters for registers must be in lower case. DO NOT TYPE DOLLAR SIGNS WITH REGISTERS. Hex Opcode (decimal) rs (decimal) rt (decimal) rd (decimal) funct (decimal) Instruction 02488822 O 18 16 17 34 sub s4 $$1 " $ to " LAComplete the following table: MIPS Instruction op code rs rt rd shamt funct imm. /address Hexadecimal Representation add $t4, $s2, $s1 addi $s0, $t0, 123 lw $s6, -88($t7) Note: In MIPS register file, temporary registers $t0-$t7 have indices 8-15 (respec- tively). Also, the saved registers $s0-$s7 have indices 16-23 (respectively).The table shows the bits shows by immediate in the different types of RISC-V assembler instructions. Write the C code , which has two arguments - 32-bit instruction and the instruction type symbol I, S, B, U, J. This function should return extracted value of immediate. for example ge t_imm_from_instr ( 0x00C48413, ‘i’ );
- Suppose the address of the first instruction is COAF3410 in hexadecimal in the following code. Show in decimal the immediate value (i.e. offset) in the beq and bne instruction, and in hexadecimal (of 7 digits) the psedudo address in the j instruction. Separate the numbers by comma. labell: beq $t1, st2, label3 (72 instructions here) label2: bne $13, st4, label1 (49 instructions here) labe 13: label2Below is the program execution's expression: X=[A*B/C]-D-[E*(F/G)] Show the one-address machine instruction.Memory 12200 12201 12202 12203 12204 Content %D AA EE FF 22 What result is produced in the destination operand by execution the following instruction? a- LEA SI[DI+Bx+5] b- LDS SI.[200]
- 3. For each instruction in the table, write 8 hexadecimal digits that represent the 32 bits in the destination register after the instruction is executed. Assume s0 is 0x98AB3C6A, s1 is 0x20503666. Instructions to, 50, s1 t1, so, s1 t2, so, s1 t3, 50, 51 addi t4, 50, 0x210 wwwwwww andi t5, 50, -16 add and or xor slli t6, 50, 12 srai s2, 50, 8 Dest. reg. in 8 hexadecimal digitsQ1:/ Show the contents in hexadecimal of registers PC, AR, DR, AC, IR and SC of the basic computer when an instruction at address 021 in the basic computer has I = 1, an operation code of the ADD instruction, and an address part equal to 051. The memory word at address 051 contains 0083. The memory word at address 083 contains B8F2. The memory word at address 038 contains A837 and the content of AC is A937. Give the answer in a table with six columns, one for each register and a row for each timing signal. (All numbers are in hexadecimal) uipors - eaIn this classification, each instruction is executed uşing its own input data, independently of how other instructions get their data. We are using a(n): A Multiple Instruction Multiple Data. B Multiple Instruction Multiple Data. C Single Instruction Single Data. D Single Instruction Multiple Data
- 26. Find the time delay in the following program if the crystal frequency is 1 MHz. Do not ignore the time delay due to the first and last instruction. DELAY: LDI R16, 30 AGAIN: LDI R17, 35 HERE: NOP NOP DEC R17 BRNE HERE DEC R16 BRNE AGAIN RETQuedT: Choose the correct answer: [ Opcode, funct3 and funct7/6 in instruction format are used to identify the: (a) function. (b) instruction. (e) branch. (d) memory address. The register that hold the address of the current instruction being executed is called: (a) saved register. (b) global pointer. (e) stack pointer. (d) program counter. Placing the executable file into the memory for execution by the processor is the role of (a) assembler. (b) linker. (e) loader. (d) compiler. The part which responsible for transmitting the data to/from the processor is: (a) control unit. (b) Datapath. (c) data bus. (d) memory. Parallel hardware cannot be used for faster division because: (a) subtraction is conditional on sign of remainder. (b) multiplication is conditional on sign of remainder. (c) subtraction is conditional on sign of divisor. (d) multiplication is conditional on sign of divisor. we cannot slower the clock cycle to fit the floating-point adder algorithm into one clock cycle…LIST P = 16F877AUsing INCLUDE "P16F877A.INC" and PWM (Pulse Width Modulation), write the microprocessor code that enables the fan to operate at 80% if the button on the 5th bit is pressed, and 30% if the button on the third bit is pressed.