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Cache system B represents a 2-way set-associative mapping cache system in table 2 The system is byte-addressable and the block size is one word (4 bytes). The tag and set numbers are represented with binary numbers. The contents of words in a block are represented with hexadecimal. Tag 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 Table 2 1. What is the size of the main memory for the Cache system B? Answer= 2. What is the size of the cache memory of Cache system B? Answer= Answer= Answer= 16 Answer= Set Number 16 1011 0110 1101 1011 0110 1101 miss(es) 1011 0110 1110 1011 0110 1110 1011 0110 1111 1011 0110 1111 1011 0111 0000 3. If we request to read memory address F1 24 2D B7, what data do we get? 1011 0111 0000 1011 0111 0001 1011 0111 0001 4. If we request to read memory address A1 24 2D B4, what data do we get? 1011 0111 0010 1011 0111 0010 Word within block 00 2016 2116 2316 2316 2416 2516 2616 2716 2816 2916 2A16 2B16 01 3016 3116 3316 3316 3416 3516 3616 3716 3816 3916 3A16 3B16 10 4016 4116 4316 4316 4416 4516 4616 4716 4816 4916 4A16 4B16 11 5016 5116 5316 5316 5416 5516 5616 5716 5816 5916 5A16 5. If we access memory in the following order in the Cache system B, how many Cache misses would occur for this data request? Assume for this question that the cache locations referenced are empty to start with Memory addresses: 1. A1 A1 FF B1 2. F1 A1 FF B2 3. A1 A1 FF B3 4. F1 A1 FF B3 5. A1 A1 FF BO 5B16

Cache system B represents a 2-way set-associative mapping cache system in table 2 The system is byte-addressable and the block size is one word (4 bytes). The tag and set numbers are represented with binary numbers. The contents of words in a block are represented with hexadecimal. Tag 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 Table 2 1. What is the size of the main memory for the Cache system B? Answer= 2. What is the size of the cache memory of Cache system B? Answer= Answer= Answer= 16 Answer= Set Number 16 1011 0110 1101 1011 0110 1101 miss(es) 1011 0110 1110 1011 0110 1110 1011 0110 1111 1011 0110 1111 1011 0111 0000 3. If we request to read memory address F1 24 2D B7, what data do we get? 1011 0111 0000 1011 0111 0001 1011 0111 0001 4. If we request to read memory address A1 24 2D B4, what data do we get? 1011 0111 0010 1011 0111 0010 Word within block 00 2016 2116 2316 2316 2416 2516 2616 2716 2816 2916 2A16 2B16 01 3016 3116 3316 3316 3416 3516 3616 3716 3816 3916 3A16 3B16 10 4016 4116 4316 4316 4416 4516 4616 4716 4816 4916 4A16 4B16 11 5016 5116 5316 5316 5416 5516 5616 5716 5816 5916 5A16 5. If we access memory in the following order in the Cache system B, how many Cache misses would occur for this data request? Assume for this question that the cache locations referenced are empty to start with Memory addresses: 1. A1 A1 FF B1 2. F1 A1 FF B2 3. A1 A1 FF B3 4. F1 A1 FF B3 5. A1 A1 FF BO 5B16

Systems Architecture
Systems Architecture
7th Edition
ISBN:9781305080195
Author:Stephen D. Burd
Publisher:Stephen D. Burd
Chapter6: System Integration And Performance
Section: Chapter Questions
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Cache system B represents a 2-way set-associative mapping cache system in table 2 The system is byte-addressable and the block size is one word (4 bytes). The tag and set numbers are represented with binary numbers. The contents of words in a block are represented with hexadecimal. Tag 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 Table 2 1. What is the size of the main memory for the Cache system B? Answer= 2. What is the size of the cache memory of Cache system B? Answer = Answer= Answer = 16 Answer = Set Number 16 1011 0110 1101 1011 0110 1101 miss(es) 1011 0110 1110 1011 0110 1110 1011 0110 1111 1011 0110 1111 1011 0111 0000 3. If we request to read memory address F1 24 2D B7, what data do we get? 1011 0111 0000 1011 0111 0001 1011 0111 0001 4. If we request to read memory address A1 24 2D B4, what data do we get? 1011 0111 0010 1011 0111 0010 Word within block 00 2016 2116 2316 2316 2416 2516 2616 2716 2816 2916 2A16 2B16 01 3016 3116 3316 3316 3416 3516 3616 3716 3816 3916 3A16 3B16 10 4016 4116 4316 4316 4416 4516 4616 4716 4816 4916 4A16 4B16 11 5016 5116 5316 5316 5416 5516 5616 5716 5816 5916 5A16 5. If we access memory in the following order in the Cache system B, how many Cache misses would occur for this data request? Assume for this question that the cache locations referenced are empty to start with. Memory addresses: 1. A1 A1 FF B1 2. F1 A1 FF B2 3. A1 A1 FF B3 4. F1 A1 FF B3 5. A1 A1 FF BO 5B16
Transcribed Image Text:Cache system B represents a 2-way set-associative mapping cache system in table 2 The system is byte-addressable and the block size is one word (4 bytes). The tag and set numbers are represented with binary numbers. The contents of words in a block are represented with hexadecimal. Tag 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 10 1000 0100 1001 0000 11 1100 0100 1001 0000 Table 2 1. What is the size of the main memory for the Cache system B? Answer= 2. What is the size of the cache memory of Cache system B? Answer = Answer= Answer = 16 Answer = Set Number 16 1011 0110 1101 1011 0110 1101 miss(es) 1011 0110 1110 1011 0110 1110 1011 0110 1111 1011 0110 1111 1011 0111 0000 3. If we request to read memory address F1 24 2D B7, what data do we get? 1011 0111 0000 1011 0111 0001 1011 0111 0001 4. If we request to read memory address A1 24 2D B4, what data do we get? 1011 0111 0010 1011 0111 0010 Word within block 00 2016 2116 2316 2316 2416 2516 2616 2716 2816 2916 2A16 2B16 01 3016 3116 3316 3316 3416 3516 3616 3716 3816 3916 3A16 3B16 10 4016 4116 4316 4316 4416 4516 4616 4716 4816 4916 4A16 4B16 11 5016 5116 5316 5316 5416 5516 5616 5716 5816 5916 5A16 5. If we access memory in the following order in the Cache system B, how many Cache misses would occur for this data request? Assume for this question that the cache locations referenced are empty to start with. Memory addresses: 1. A1 A1 FF B1 2. F1 A1 FF B2 3. A1 A1 FF B3 4. F1 A1 FF B3 5. A1 A1 FF BO 5B16
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