Draw the memory map and show the values of the affected registers and memory locations, assuming AC initial value given below at the execution of each instruction. Sn instruction 1 1000000111100001 2 1101000111100010 3 0111001000111111 4 1110000111100011 Information and hint M[1E3] =125, M [235] =126, M[1E1] =127, M[1E2] =123, M[1E4] =128, M[0A4] =1E1, Initially AC=0CF1
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- The time it takes to perform the fetch instruction and decode instruction steps is called the execution time. True or false?Complete the following table: MIPS Instruction op code rs rt rd shamt funct imm. /address Hexadecimal Representation add $t4, $s2, $s1 addi $s0, $t0, 123 lw $s6, -88($t7) Note: In MIPS register file, temporary registers $t0-$t7 have indices 8-15 (respec- tively). Also, the saved registers $s0-$s7 have indices 16-23 (respectively).Consider the instruction ADD R1, M (R1 = R1 + [M]). M is the memory address of the operand. It is a two-word instruction – first word is the op-code and the second word is the address of the operand. Give the RTL description for the complete execution (including fetch phase) of the instruction.
- A two-word instruction is stored in memory at an address designated by the symbol A. The address field of the instruction (stored at A + 1) is designated by the symbol Y. The operand used during the execution of the instruction is stored at an address symbolized by EA. An index register contains the value X. With the help of diagram, state how EA is calculated from the other addresses if the addressing mode of the instruction is (1)- direct (2)- indirect (3)- indexed (4)-Relative (5)- Register indirect3. Let say BX = 1000H, SI = 2000H, DISP = 1234H, DS =1200H. %3D Determine the effective address of the Word that will be transferred to DX when executing this instruction: MOV DX,[BX+SI+1234]3. For each instruction in the table, write 8 hexadecimal digits that represent the 32 bits in the destination register after the instruction is executed. Assume s0 is 0x98AB3C6A, s1 is 0x20503666. Instructions to, 50, s1 t1, so, s1 t2, so, s1 t3, 50, 51 addi t4, 50, 0x210 wwwwwww andi t5, 50, -16 add and or xor slli t6, 50, 12 srai s2, 50, 8 Dest. reg. in 8 hexadecimal digits
- Identify the addressing modes & the value of the register Ro for each of given instructions if initial values of Ro= 1500, R1=3000, PC = 4000. ADDRESS VALUE 1000 1260 2000 1570 2900 1400 3000 1650 4000 1750 4102 1150 4500 1760 5000 1850 i) Ld Ro. #125 11) Ld. Ro. [3000] i11) Ld Ro. [Ri] iv) Ld Ro. -100[Ri] v) Ld Ro. [PC+100]Consider a 16-bit processor in which the following appears in main memory, starting at location 200: B. The first part of the first word indicates that this instruction loads a value into an accumulator. The mode field specifies an addressing mode and if appropriate, indicates a source register; Assume that when used, the source register is R1, which has a value of 400. There is also an index register (XR) that contains 100. The value of 500 in location 201 may be part of the address calculation. Assume that location 399 contains the value 999, location 400 contains the value 1000, and so on. Determine the effective address and the operand to be loaded for the following address modes:Q1. Write microcode for the execution part of the following CISC instruction. Give both a register transfer description and binary or hexadecimal representations. Add with carry: R[DR] + R[SA]+R[SB]+c Action Address MZ CA RW DX MD BS PS FS LC MA MB AX BX CS
- Q: Compute the physical address for the specified operand in each of the following instructions. The register contents and variable are as follows: (CS)=0A00H, (DS)=0B00H, (SS)=0D00H, (SI)=OFFOH, (DI)=00BOH, (BP)=00EAH and (IP)=00O0H, LIST=00FOH, AX=4020H, BX=2500H. 1) Destination operand of the instruction MOV LIST [BP+DI] , AX 2) Source operand of the instruction MOV CL, [BX+200H] 3) Destination operand of the instruction MOV [DI+6400H] , DX 4) Source operand of the instruction MOV AL, [BP+SI-400H] 5) Destination operand of the instruction MOV [DI+SP] , AX 6) Source operand of the instruction MOV CL, [SP+200H] 7) Destination operand of the instruction MOV [BX+DI+6400H] , CX 8) Source operand of the instruction MOV AL , [BP- 0200H] 9) Destination operand of the instruction MOV [SI] , AX 10) Destination operand of the instruction MOV [BX][DI]+0400H,AL 11) Source operand of the instruction MOV AX, [BP+200H] 12) Source operand of the instruction MOV AL, [SI-0100H] 13) Destination operand…Evaluate the effect of the instruction LDR r5, [r7, #4], given the initial values below. Give the final values of all the registers. Registers: r5 = 100 r6 = 1000 r7 = 996 Memory Address Value 992 30 996 40 1000 50 1004 60 1008 70 O r5=50, r6=1000, r7=1000 O r5=40, r6=1000, r7=996 O r5=40, r6=1000, r7=1000 O r5=50, r6=1000, r7=996Q1:/ Show the contents in hexadecimal of registers PC, AR, DR, AC, IR and SC of the basic computer when an instruction at address 021 in the basic computer has I = 1, an operation code of the ADD instruction, and an address part equal to 051. The memory word at address 051 contains 0083. The memory word at address 083 contains B8F2. The memory word at address 038 contains A837 and the content of AC is A937. Give the answer in a table with six columns, one for each register and a row for each timing signal. (All numbers are in hexadecimal) uipors - ea