figure below shows an 8-way interleaved, byte-addressable memory. The total size of the memory is 4 KB. The elements A[i]G) of a 2-dimensional array A are 4-bytes (one-word) in length and can be stored in the memory as shown, where 0

Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
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4. The figure below shows an 8-way interleaved, byte-addressable memory. The
total size of the memory is 4 KB.
The elements A[i]G) of a 2-dimensional array A are 4-bytes (one-word) in length
and can be stored in the memory as shown, where 0 < ij <7.
The width of the bus between CPU and memory is 32 bits, that is, it can carry
only one word at a time.
Bank 1
Bank 7
Bank 0
31
7
A[7][0]
A[I][0]
A[0]|0]
32
A[7]1]
64
A[7]|2]
A[I][2]
A[0||2]
RANKO
255
224
AI기기
A[I][7]
A[0||7)
RANKN
......
Since the address space of the memory is 4 KB, 12 bits are needed to uniquely
identify each memory location, i.e., Addr[11:0]. Find out and explain which bits
of the address will be used for:
• Byte on bus: Addr […... :...]
Bank index bits within a bank: Addr [.... .]
• Chip select address bits within a rank: Addr […... .]
• Rank bits: Addr […... :....]
Transcribed Image Text:4. The figure below shows an 8-way interleaved, byte-addressable memory. The total size of the memory is 4 KB. The elements A[i]G) of a 2-dimensional array A are 4-bytes (one-word) in length and can be stored in the memory as shown, where 0 < ij <7. The width of the bus between CPU and memory is 32 bits, that is, it can carry only one word at a time. Bank 1 Bank 7 Bank 0 31 7 A[7][0] A[I][0] A[0]|0] 32 A[7]1] 64 A[7]|2] A[I][2] A[0||2] RANKO 255 224 AI기기 A[I][7] A[0||7) RANKN ...... Since the address space of the memory is 4 KB, 12 bits are needed to uniquely identify each memory location, i.e., Addr[11:0]. Find out and explain which bits of the address will be used for: • Byte on bus: Addr […... :...] Bank index bits within a bank: Addr [.... .] • Chip select address bits within a rank: Addr […... .] • Rank bits: Addr […... :....]
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