For the circuit shown below (ß1=B2=150), determine: - 1. the de values (V81, V82, Vc1, Vc2, Ve1, Ve2, Vce1, Vce2). 2. The Zi, Zo, Ay NL, Av_L, Avs· Vcc 9 18 V R1 39 kN Rc 3 3.3 k2 Vo V82 Q Vc R2 $5.1 kN RL34.7 kn 1 kN Rs Vs R3 310 k2 Rei 322 N RE 31.3 kN
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Q: For the circuit shown below (B1=B2=150), determine: - 1. the de values (V81, V82, Vc1, Vc2, Ve1,…
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Q: For the circuit shown below (ß1=B2=150), determine: - 1. the de values (V81, V82, Vc1, Vc2, VE1,…
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Q: For the circuit shown below (B1=B2=150), determine: - 1. the de values (V81, V82, Vc1, Vc2, VE1,…
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- a) Draw and explain the equivalent circuit and V-I characteristics of the UJT in detail. b) A UJT circuit is shown in figure 2. The parameters of the UJT are n = 0.65 and RBB = 7 km. i. Find RBI and RB2. ii. Determine the value of VB1B2 and Vp. R₂ R₂ 400 £2 B₂ 20 100 £2 Figure 2Implement the digital circuit as illustrated in Figure Q2 using data-flow method in VHDL and use comments in the program to support your answer. C D. B' D- C' Figure Q2For the circuit shown above, it is given that: R1= 15, R2= 7, R3 = 9, R4 = 5, R5 = 13, and RL = 8. If V1 = 34 and V2 = 22, find the load current IL.
- A Wheatstone bridge is used for measuriug the valuc of change of resistance of a strain gauge wnich forms one of the arms of the bridge. All tbe arms of the bridge including the strain gauge have a resistance of 100 N each. The maximum a!lowable power dissipation from the strain gauge is 250 mW. Determine the value of maximu:n permissible current through the strain gauge and maximum allowable value of bridge supply voltage. Suppose a source of 20 V is available, lind the value of series resistance to be connected between the source and the bridge to limit the input voltage of the bridge to permissible level.Q2): The N-bit DAC with an (R-2R) ladder network is to be designed as a 6-bit DAC device. Let (VREF= -5 V and R=RF=5 k2). (a) What are currents (I1, I2, l3, 14, I5, and I6)? (b) The input changes by 1 LSB. What is the change in the output voltage? (c) What is the output voltage if the input is (010011)? (d)What is the change in output voltage if the input changes from (101010 to 010101)?transform the circuit in phasor domain representation a) Determine the value of branch current, I1 and I2b) Determine the value of voltage across resistor, R1, R2 and R3c) Determine the value of voltage across capacitor, C1 and C2d) Determine the value of voltage across inductor, L.
- 1. Obtain the state diagram and a primitive flow table for a circuit with two inputs X1 and X2 and two output Zland Z2 that satisfies the following four conditions:- i) When X1X2 =00 output Z1Z2=00. ii) When X1=1 &X2 changes from 0 tol, the output Z1z2 =01. iii) When X2=1 &X1changes from 0 to 1, the output Zizz=10. iv) Otherwise the output does not change 2. Design an asynchronous sequential circuit with two inputs X1 and X2 and one output Z. The output goes to 1 at the end of the input sequence 01=> 11 => 10. Then the output will return to zero. No other sequences cause output to go to 1. 3- Design a 3-bit simultaneous ADC with a full-scale output equal to (10 v) using a clock frequency of 1MHZ. 1- Draw the circuit diagram. 2- Write the table represents the values of the input voltage, comparator output and binary output for this circuit. 3- Find the equations of the binary output bits, i.e., the equations of MSB, 2nd bit and LSB. 4- Find the digital conversion of the analogue…1. Obtain the state diagram and a primitive flow table for a circuit with two inputs X1 and X2 and two output Zland Z2 that satisfies the following four conditions:- i) When X1X2 =00 output Z1Z2=00. ii) When X1=1 &X2 changes from 0 tol, the output Z1z2 =01. iii) When X2=1 &X1changes from 0 to 1, the output Z1Z2=10. iv) Otherwise the output does not changeb) Use the ALU 74181 in the figure below and the tables (one is enough; second maybe, need to check the new kit) to implement : A + B, A – B, A. B. (MSB) (LSB) 10 (MSB) F3 F2 F1 FO S3 Cn+4 16 s2 20 U14 15 S1 14 so A3 A2 A1 AO B3 B2 B1 B0 M Cn 24 23 22 21 28 27 T26 25 (LSB) (MSB) (LSB)(MSB) (LSB) And given that under M = 1 the circuit performs the following arithmetic and logic functions according to Table 11.1. Input selection S3 Output M-H S2 SI Cn=L. F3 F2 F1 FO A 1 -A В -B A&B AxB 1 A'B 1 Ax(-B) (-A)xB (-A)x(-B) 1 1 ACTIVE HIGH DATA M-L: ARITHMETIC OPERATIONS SELECTION M-H LOGIC s3 s2 s1 so Ino carry) (with carry) F-A PLUS 1 F- LA + B) PLUS 1 F- (A + BI PLUS 1 FUNCTIONS L L F-A F-A+B F-AB F-A H FA+B F-A+T F- MINUS 1 12s COMPL) F-A PLUS AB F- IA + BI PLUS AB L L L L F-0 F-ZERO F- AB F-A PLUS AB PLUS 1 F- (A + BI PLUS AB PLUS 1 L L L H L F-AOB F- AB L L F-A MINUS B MINUS 1 F-A MINUS B F- AB MINUS 1 F- A F-A PLUS AB PLUS1 F-A PLUS B PLUS 1 F- IA + B PLUS AB PLUS 1 L H L F-A PLUS AB…
- Show that the convolution between Acoswt and coswt is Atcoswt. *I have a quetion about this problem. How can I show 'the convolution between Acoswt and coswt is Atcoswt' using L'Hopital's rule? .Write down at least three reasons which cause difference between R1 (R2) and R = Vmes/imes values in the below table?Provide circuit diagram for following equations: AB’{C+D’}’+{G.H}’+{A xor M} {{M+N}’.{Q xnor P’}.{A’.C’}’}