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Memory Performance: The following questions will refer to the same instruction mix as above, with the following additional information: Processor P1: 42% of all instructions are memory access instructions. Level 1 Cache Access=0.68 ns GHz. Main Memory Access = 59 ns 12% of all memory access is a "miss". 9. The clock rate of the processor = 10 The Average Memory Access Time for the given data = nsament smua ort orig cycles 11. The Average number of cycles for a memory access = 12. Assuming that the base CPI = 1.0 cycles, and using the answer from #11, memalquiew 110 the average time to complete an instruction for the program described = Now, consider processor P2, with the addition of a Level 2 Cache, with an access time of 4.3 ns and a "hit" rate of 13%. 13. The Average Memory Access Time for the given data = 14. The Average number of cycles for a memory access = cycles 15. Assuming that the base CPI = 1.0 cycles, and using the answer from #14, the average CPI for the program described cycles o 16. Which processor performs better for the program described? (P1 or P2) ns 17. Including the delays in the Pipelined DataPath in question 8, and the memory performance analysis in question 15, find the Average Memory Access = 18. Find the final average effective number of cycles for processor P2 = 19. Find the final average time to complete an instruction for processor P2 = ns for P2. 0-31 ns

Memory Performance: The following questions will refer to the same instruction mix as above, with the following additional information: Processor P1: 42% of all instructions are memory access instructions. Level 1 Cache Access=0.68 ns GHz. Main Memory Access = 59 ns 12% of all memory access is a "miss". 9. The clock rate of the processor = 10 The Average Memory Access Time for the given data = nsament smua ort orig cycles 11. The Average number of cycles for a memory access = 12. Assuming that the base CPI = 1.0 cycles, and using the answer from #11, memalquiew 110 the average time to complete an instruction for the program described = Now, consider processor P2, with the addition of a Level 2 Cache, with an access time of 4.3 ns and a "hit" rate of 13%. 13. The Average Memory Access Time for the given data = 14. The Average number of cycles for a memory access = cycles 15. Assuming that the base CPI = 1.0 cycles, and using the answer from #14, the average CPI for the program described cycles o 16. Which processor performs better for the program described? (P1 or P2) ns 17. Including the delays in the Pipelined DataPath in question 8, and the memory performance analysis in question 15, find the Average Memory Access = 18. Find the final average effective number of cycles for processor P2 = 19. Find the final average time to complete an instruction for processor P2 = ns for P2. 0-31 ns

Programming Logic & Design Comprehensive
Programming Logic & Design Comprehensive
9th Edition
ISBN:9781337669405
Author:FARRELL
Publisher:FARRELL
Chapter12: Event-driven Gui Programming, Multithreading, And Animation
Section: Chapter Questions
Problem 17RQ
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Please help with this Computer architecture homework question.
Memory Performance: The following questions will refer to the same instruction mix as above, with the following the additional information: Processor Pl: 42% of all instructions are memory access instructions. Level 1 Cache Access = 0.68 ns GHz. Main Memory Access = 59 ns 12% of all memory access is a "miss". 9. The clock rate of the processor = _cycles 10 The Average Memory Access Time for the given data = 11. The Average number of cycles for a memory access 12. Assuming that the base CPI = 1.0 cycles, and using the answer from #11, memolqui w 110 ad bloow slova ono lo digasi or ns the average time to complete an instruction for the program described =_ Now, consider processor P2, with the addition of a Level 2 Cache, with an access time of 4.3 ns and a "hit" rate of 13%. ii.nontasmalami bonil ns 13. The Average Memory Access Time for the given data = 14. The Average number of cycles for a memory access = 15. Assuming that the base CPI = 1.0 cycles, and using the answer from #14, the average CPI for the program described 16. Which processor performs better for the program described? (P1 or P2) nsonment scusa origied 2 ns for P2. cycles and musta neljastui buol top-31 cycles gydommel 17. Including the delays in the Pipelined DataPath in question 8, and the memory performance analysis in question 15, find the Average Memory Access = 18. Find the final average effective number of cycles for processor P2 = 19. Find the final average time to complete an instruction for processor P2 = Jani 100 astig on de 1o A is endowand Iho-stiupst GODE
Transcribed Image Text:Memory Performance: The following questions will refer to the same instruction mix as above, with the following the additional information: Processor Pl: 42% of all instructions are memory access instructions. Level 1 Cache Access = 0.68 ns GHz. Main Memory Access = 59 ns 12% of all memory access is a "miss". 9. The clock rate of the processor = _cycles 10 The Average Memory Access Time for the given data = 11. The Average number of cycles for a memory access 12. Assuming that the base CPI = 1.0 cycles, and using the answer from #11, memolqui w 110 ad bloow slova ono lo digasi or ns the average time to complete an instruction for the program described =_ Now, consider processor P2, with the addition of a Level 2 Cache, with an access time of 4.3 ns and a "hit" rate of 13%. ii.nontasmalami bonil ns 13. The Average Memory Access Time for the given data = 14. The Average number of cycles for a memory access = 15. Assuming that the base CPI = 1.0 cycles, and using the answer from #14, the average CPI for the program described 16. Which processor performs better for the program described? (P1 or P2) nsonment scusa origied 2 ns for P2. cycles and musta neljastui buol top-31 cycles gydommel 17. Including the delays in the Pipelined DataPath in question 8, and the memory performance analysis in question 15, find the Average Memory Access = 18. Find the final average effective number of cycles for processor P2 = 19. Find the final average time to complete an instruction for processor P2 = Jani 100 astig on de 1o A is endowand Iho-stiupst GODE
PC 41 Add Read address Instruction [31-0] Instruction memory it jugust slave oldoly gjuar slovo-ulgrier Instruction [31-26] Instruction [25-21] Instruction [20-16] Instruction [15-11] Control Instruction [15-0] RegDst Branch MemRead MemtoReg ALUOP MemWrite ALUSrc RegWrite Read register 1 Read data 1 Read register 2 Write Read register data 2 Write data Registers 16 Sign- extend 32 Instruction [5-0] Shift left 2 0 MUX hoito aq 01E=anoihinago 03/ a die led od ALU Add, result ALU control Zero ALU ALU result M malqi sw 11.1 1 Jollót edt 10l smit SOY SC 2 Read Address data Write Data data memory OXCM qmul bood
Transcribed Image Text:PC 41 Add Read address Instruction [31-0] Instruction memory it jugust slave oldoly gjuar slovo-ulgrier Instruction [31-26] Instruction [25-21] Instruction [20-16] Instruction [15-11] Control Instruction [15-0] RegDst Branch MemRead MemtoReg ALUOP MemWrite ALUSrc RegWrite Read register 1 Read data 1 Read register 2 Write Read register data 2 Write data Registers 16 Sign- extend 32 Instruction [5-0] Shift left 2 0 MUX hoito aq 01E=anoihinago 03/ a die led od ALU Add, result ALU control Zero ALU ALU result M malqi sw 11.1 1 Jollót edt 10l smit SOY SC 2 Read Address data Write Data data memory OXCM qmul bood
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