Please answer the following based on these instructions; The below microarchitecture diagram has three independent control lines (Reg Dest, Reg Input, ALU Input) control individual multiplexers that were previously controlled together by a single control line named Mem This allows us to add a new instruction, ADDC, which stands for "Add Constant" ADDC Rs, const, Rt adds the contents of source register Rs to the two's complement constant value const, given by the instruction, and stores the sum in destination register Rt. For example, ADDC R2, 3, R4 stores into register R4 the result of adding the constant 3 to the contents of register R2; ADDC R0, -1, R2 stores 0x1111 into register R2 (because 0+-1=-1) a) What values do registers R5 and R6 hold after the following program runs? R1 always holds 1; R5 and R6 are general purpose registers ADD R1, R1, R5 ADD R1, R5, R6 ADDC R6, 4, R5 HALT b) Show the concrete encoding of the ADDC R6, 4, R5 instruction
Please answer the following based on these instructions; The below microarchitecture diagram has three independent control lines (Reg Dest, Reg Input, ALU Input) control individual multiplexers that were previously controlled together by a single control line named Mem This allows us to add a new instruction, ADDC, which stands for "Add Constant" ADDC Rs, const, Rt adds the contents of source register Rs to the two's complement constant value const, given by the instruction, and stores the sum in destination register Rt. For example, ADDC R2, 3, R4 stores into register R4 the result of adding the constant 3 to the contents of register R2; ADDC R0, -1, R2 stores 0x1111 into register R2 (because 0+-1=-1) a) What values do registers R5 and R6 hold after the following program runs? R1 always holds 1; R5 and R6 are general purpose registers ADD R1, R1, R5 ADD R1, R5, R6 ADDC R6, 4, R5 HALT b) Show the concrete encoding of the ADDC R6, 4, R5 instruction
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
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Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Please answer the following based on these instructions;
The below microarchitecture diagram has three independent control lines (Reg Dest, Reg Input, ALU Input) control individual multiplexers that were previously controlled together by a single control line named Mem This allows us to add a new instruction, ADDC, which stands for "Add Constant" ADDC Rs, const, Rt adds the contents of source register Rs to the two's complement constant value const, given by the instruction, and stores the sum in destination register Rt. For example, ADDC R2, 3, R4 stores into register R4 the result of adding the constant 3 to the contents of register R2; ADDC R0, -1, R2 stores 0x1111 into register R2 (because 0+-1=-1)
a) What values do registers R5 and R6 hold after the following program runs? R1 always holds 1; R5 and R6 are general purpose registers
ADD R1, R1, R5
ADD R1, R5, R6
ADDC R6, 4, R5
HALT
b) Show the concrete encoding of the ADDC R6, 4, R5 instruction
![Shift loft by 16 Zero
extend
01
Jump
>+
Instruction
Memory
Read
Address
Inst
Reg Dest
ADD Rs, Rt, Rd
LW Rt, offset (Rs)
SW Rt, offset (Rs)
(15:12)
(11:8)
16 (7:4)
(3:01
Reg Input
Control
Unit
ALU Input
white frable
Read Addr 1
Read Addr 2
Reg Write
Write Addr
16 Write Data
Read
Data 1
Register File
Read
Data 2
Sign extend
R[d] ← R[s] + R[t]
R[t] ← M[R[s] + offset]
M[R[s] + offset] ← R[t]
New: ADDC Rs, const, Rt | R[t] ←- R[s] + const
Shift left by
Branch
ALU
Control
>ALU
S
S
S
S
zero flag
16
Mem Store
t
t
t
t
Address
Data Memory
Write
Data
We will extend the microarchitecture with ADDC by choosing an instruction encoding like so:
Syntax
Meaning
[15:12] [11:8] | [7:4]| [3:0]
opcode
0010
0000
0001
1101
Write Enable
d
offset
offset
const
Read
Data
0 1](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F9fc5cf3b-131f-4b96-b841-53f4b4b8e72f%2F552f1c2d-1bd8-4154-9ea6-f61ff428eefd%2Fgqa6gj_processed.jpeg&w=3840&q=75)
Transcribed Image Text:Shift loft by 16 Zero
extend
01
Jump
>+
Instruction
Memory
Read
Address
Inst
Reg Dest
ADD Rs, Rt, Rd
LW Rt, offset (Rs)
SW Rt, offset (Rs)
(15:12)
(11:8)
16 (7:4)
(3:01
Reg Input
Control
Unit
ALU Input
white frable
Read Addr 1
Read Addr 2
Reg Write
Write Addr
16 Write Data
Read
Data 1
Register File
Read
Data 2
Sign extend
R[d] ← R[s] + R[t]
R[t] ← M[R[s] + offset]
M[R[s] + offset] ← R[t]
New: ADDC Rs, const, Rt | R[t] ←- R[s] + const
Shift left by
Branch
ALU
Control
>ALU
S
S
S
S
zero flag
16
Mem Store
t
t
t
t
Address
Data Memory
Write
Data
We will extend the microarchitecture with ADDC by choosing an instruction encoding like so:
Syntax
Meaning
[15:12] [11:8] | [7:4]| [3:0]
opcode
0010
0000
0001
1101
Write Enable
d
offset
offset
const
Read
Data
0 1
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