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- Design a combinational circuit with the four inputs A,B.C, and D, and three outputs X, Y, and Z. When the binary input is odd number, the binary output is one lesser than the input. When the binary input is even number the binary output is one greate than the input. Implement the function using multiplexers with minimal input and select line.Design a combinational circuit that takes 3-bit pattern as input and outputs binary code of bit position of the first 1' in the pattern reading from MSB (2nd position) to LSB (0th position).An additional output variable V is required along with binary code to indicate that the binary code is valid or note i.e., if the input pattern is '000' then the output V should be '0' to indicate that the binary code is not indicating the bit position of first 1' and we don't care about the binary code if V = 0. Design the required circuit using dual 4x1 MUXS and minimum additional logic.Available resources along with dual 4x1 MUXS are NOT gates, 2-input(AND, OR, NAND, NOR) gates.A. Write a Verilog HDL code for Verilog code for a for 6-bit unsigned up counter B. Write test bench code of the circuit in the figure: DỊ40) 5-bit Full Adder 5-bit 5-bit Up - Counter DFF Ck
- A 10-bit ADC with Viet - 3.1 V has a step size equal to mV (you have to write 2 digits after the decimal point.. not.) for Vin=28% the output is equal to NB to obtain the digital result you have to use the value of the step size filled in the first part of the question- The proportional distribution of A, B, C, D signals is given in the table as a percentage. It “logic 1” when the signals are accepted as active, “logic 0” when they are accepted as passive. takes. - When the proportional sum of active signals is over 50%, its output is "logic1", When we accept "logic 0" when it is below 50%, the output in the table Find the values. - Create an X function based on the logic values you find. Simplify the created X function. - Design the simplified function with NAND and NOR gates.- The proportional distribution of A, B, C, D signals is given in the table as a percentage. It “logic 1” when the signals are accepted as active, “logic 0” when they are accepted as passive. takes. - When the proportional sum of active signals is over 50%, its output is "logic1", When we accept "logic 0" when it is below 50%, the output in the table Find the values. - Create an X function based on the logic values you find. Simplify the created X function. - Design the simplified function with NAND and NOR gates. - Set up the circuits you designed with NAND and NOR gates and observe the outputs. Show the output values by drawing a table, applying all possibilities to the input values.
- (b) Consider a voice signal from a analog telephone which needs to be digitized. Explain the steps involved in the conversion of analog to digital signal. If suppose the sampled analog values are 1V, 2V, 3.5V and 4.5V, use a 2 bit quantizer to digitize these values. Assume the range of sampled analog values from 0V to 5V. Provide the digitized values of this signal and draw the digital signal.Q2) A) Express the decimal number (- 30 ) as an 8-bit number in 2's complement form, and verifying its decimal value. B) Design an Octal-to-Binary (8-to-3) Encoder, and then draw a block diagram for Octal-to- Binary Encoder.DFF circuit that adds the one-bit numbers a and b in series. Design according to the Mealy model a)state diagram b)state table c)simplification with Karnaugh maps
- Design the interfacing circuit shown below and write a program to display single digit (between 0 and 9) prime numbers followed by even numbers, the next odd numbers and repeats in 7-segment displays and its equivalent 8-bit binary value in LEDS. a) When displaying Prime numbers, the first 7-segment display must show "P" and the second 7-segment display must show prime numbers one by one b) When displaying Even numbers, the first 7-segment display must show "E" and the second 7-segment display must show even numbers one by one c) When displaying Odd numbers, the first 7-segment display must show "O" and the second 7-segment display must show even numbers one by oneA 12-bit ADC unit has an input voltage range of -ve 5to +ve 5 VDC. What is the minimum difference in voltage required by an analogue signal for the digitally converted value to reflect that change(resolution)? 0.0012V DC b. None of all 0.083V DC C. 0.0024V DC 4Consider Analog to Digital Converters, calculate the following for a 3-bit quantizer with a range from -5 to 5 V. a) How many levels does this ADC have? b) Determine the quantization step size c) Determine the quantization error d) In case the accuracy required imposes a quantization error less than 4 mV, what is the specification needed for the used ADC?