SI Sh L CLK D3 00 01 11 03 DQ D₂ 00 DQ D₁ º DQ (b) Implementation using flip-flops and MUXes Do 00 11 o DQ

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Author:James Kurose, Keith Ross
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Redesign the right-shift register circuit of figure 12-10 using 4 D flip-flops with clock enable, four 2-to-1 MUXes, and a single OR gate

SI
Sh
L
CLK
D3
00
01
10
11
23
DQ
D2
00
01
10
11
Q₂
DQ
D₁
00
01
10
11
2₁
DQ
(b) Implementation using flip-flops and MUXes
Do
00
01
10
11
20
DQ
Transcribed Image Text:SI Sh L CLK D3 00 01 10 11 23 DQ D2 00 01 10 11 Q₂ DQ D₁ 00 01 10 11 2₁ DQ (b) Implementation using flip-flops and MUXes Do 00 01 10 11 20 DQ
FIGURE 12-10
Parallel-In,
Parallel-Out
Right-Shift
Register
Cengage Learning 2014
SI (Serial In)
Sh (Shift Enable)
L (Load Enable).
CLK
Parallel Output
Q3 Q2 Q1 Qo
4-bit Parallel-In,
Parallel-Out
Shift Register
D3 D2 D1 Do
Parallel Input
(a) Block diagram
-SO (Serial Out)
Transcribed Image Text:FIGURE 12-10 Parallel-In, Parallel-Out Right-Shift Register Cengage Learning 2014 SI (Serial In) Sh (Shift Enable) L (Load Enable). CLK Parallel Output Q3 Q2 Q1 Qo 4-bit Parallel-In, Parallel-Out Shift Register D3 D2 D1 Do Parallel Input (a) Block diagram -SO (Serial Out)
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