5. Use the priority list T1, T3, T4, T6, T2, TS, T8, T7 schedule the project below with two processors. Task Tasks that must be completed first. Time Required (days) 6. TI T2 5 T3 T4 10 TI, T2 TS 9. T4 T6 7 T3 T7 TS T8 12 T6
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- _____ is a CPU design technique in which instruction execution is divided into multiple stages and different instructions can execute in different stages simultaneously.1. Anna designs a 2.5 GHz processor where two important programs, A and B, take onesecond each to execute. Each program has a CPI of 1.25. Elsa is tasked with designingthe company's next-generation processor and she comes up with an idea that improvesthe CPI of A to 1.1 and the CPI of B to 0.9. But the idea is so complex that theprocessor can only be implemented with a cycle time of 0.5 ns. Does Elsa's newprocessor out-perform Anna's processor on program A? How about on program B?2. Consider two different implementations of the same instruction set architecture. Theinstructions can be divided into four classes according to their CPI (class A, B, C, andD). P1 with a clock rate of 2.5 GHz and CPIs of 1, 2, 3, and 3, and P2 with a clockrate of 3 GHz and CPIs of 1, 2, 2, and 2.Given a program with a dynamic instructioncount of 106 instructions divided into classes as follows: 10% class A, 20% class B,50% class C, and 20% class D, which is faster: P1 or P2?Define pipelining in terms of increasing the speed of a processor, and then determine how many cycles it would take to run five instructions if each part of the machine required the same amount of time. In the absence of pipelining With pipelining, you may do (a), (b), (c), and (d), respectively.
- computer architecture Assume that the operation times of one add instruction for the major functional units are 325 ps for memory access, 185 ps for ALU operations and 125 ps for register file read/writes. Please fill the table first and perform the following a )What is the total cycle in single-cycle implementation? b )What is the total cycle in pipelining implementation? c) What is the total cycle in pipelining implementation if there are 5 million add instructions? d) What is the total cycle in pipelining implementation for 5 million add instructions, if the stages are balanced? e)What is the speed up of pipelining implementation over single-cycle implementation?P1, P2, P3 process are executing 2sec for Processor-bound and 2sec for 1/O bound execution. Process P1, P2, P3 are repeating this execution format for 4times,2times,3times respectively. Find the CPU utilization with multi-programming and without multi-programming and justify your answer.A Program is running on a processor Pl and it has the following parameters: Ic is equal to 20,000,000 instructions Average CPI is 3 cycles/instruction CPU frequency is 500 MHz A new processor P2 is used with the following parameters and the program is executed on this new processor now: Ic is equal to 18,000,000 instructions New average CPI: 3.5 cycles/instruction CPU new frequency: 600 MHz Which processor is faster? Compute the speedup.
- Registers are fast, but small memory locations that are inside of a CPU. They are used for the CPU's internal computations. A modern 32-bit CPU only contains 8 registers that we are capable of manipulating: EAX, EBX, ECX, EDX, EBP, ESP, ESI, and EDI. Each of these is a 32-bit register (meaning they each hold 32 digit binary numbers). There are many situations where we would want to use smaller portions of data than 32 bits. For example, when working with characters we are primarily using byte data, since each character is stored in just a single byte (which you should know is 8 bits). For this purpose, portions of the 32-bit registers can be referenced directly as if they were smaller registers. The register EAX holds 32-bits. The register AX is the bottom half of EAX, holding just 16 bits. The register AL is the bottom half of AX, holding just 8 bits. There is also AH, which is the top half of AX and also holds 8 bits. EBX, ECX, and EDX can also be split up in the same manner using…The architecture of a CPU may consist of a universal register, a singular accumulator, or a stack. Each has benefits and drawbacks. Your response could be correct or incorrect.Single instruction computer (SIC) has only one instruction that for all operations our MIPS does. The instruction has the following format. sbn a, b, c # Mems[a]=Mem[a]- Mem[b]; if (Mem[a]<0) go to PC+c For example, here is the program to copy a number from location a to location b: Start: sbn temp, temp, 1 sbn temp, a, 1 sbn b, b, 1 sbn b, temp, 1 So build SIC program to add a and b, leaving the result in a and leaving b unmodified.
- A Program is running on a processor P1 and it has the following parameters: Ic is equal to 20,000,000 instructions Average CPI is 3 cycles/instruction CPU frequency is 500 MHz A new processor P2 is used with the following parameters and the program is executed on this new processor now: Ic is equal to 18,000,000 instructions New average CPI: 3.5 cycles/instruction CPU new frequency: 600 MHz Which processor is faster? Compute the speedup.10. The register content for an Intel 8086 microprocessor is as follows:CS = 5000H, DS = 6000H, SS = 7000H, SI = 8000H, DI = 9000HBX = 4A1FH, BP = 3000H, AX = 3597H, CX = 19DAH, DX = 8B73HCalculate the physical address of the memory where the operand is stored and thecontents of the memory locations in each of the addresses shown below:a) MOV [BP + 58], AXb) MOV [SI][BX]+2FH, DXc) MOV [DI][SI]+49AH, DX1. Draw the complete block diagram for an 8086 Microprocessor system with 8-push button switches and 8-LEDS in detail assuming the input/output (I/O) address is (33h). 2. Redraw the same block diagram if you have 32-switches and 32 -LEDS, starting with the I/O address (1O0h), then write a program to read the switch states and output them to the LEDS in accordance (one to one).