1. Design or Draw a "3 to 8" decoder. Add (1) enable pin as an input to control when your design is active. 2. Derive equations from your truth table (0.5) 3. What application could this be used in? (0.5) DO A 2x4 D1 Decoder B D2 D3 Add a control pin (enable) A B YO Y1 Y2 Y3 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 10 1 0 1 1 0 0 0 1 Derive the equations
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- Draw a symbol for a solid-state logic element AND.1- Explain the operation of the PCM encoder used in module ED-2960F. 2- Discuss the advantages and disadvantages of the counter-type ADC. 3- Is the conversion time of the ADC constant or variable? What parameter does control it? 4- What are other types of ADCS? 5- Discuss the effect of changing the number of bits on the recovered analogir I need the solution step by step and clear line please Example Assuming that a 3-bit ADC channel accepts analog input ranging from 0 to 5volts, determine a- The number of quatization levels b- The step size of the quantizer or resolution. c- The quantization level when the analog voltage is 3.2 volts. d- The binary code produced by the ADC. e- The quatization error when the analog voltage is 3.2 volts.
- Write VHDL code for a modulo-13 counter (counting sequence is 010, 110, …. 1210). The counter has the following features: a synchronous Active High Reset a value R can be loaded into the counter, using the signal Ld (Load) The signal Ld is active High Draw the schematic of your counter, showing the inputs and outputs. Show the number of bits for R, Q (output of the counter), Ld.1. What is the modulo of the circuit below? 2. Make a table of the count sequence. 3. A BCD counter can assume____discrete state. 4. A BCD counter can divide its input frequency by____. 5. A four-bit binary counter contains the number 0100. Nine inpulse occur. The new counter state is_____. 6. Design a 4-bit down counter.draw the curcuit diagram for 4 channel 4 bit multiplexer implemented using 4 channel 1 bit multiplexer. make sure that i need full circuit to save the final multiplexer in the library.
- Example Assuming that a 3-bit ADC channel accepts analog input ranging from 0 to 5volts, determine a- The number of quatization levels b- The step size of the quantizer or resolution. c- The quantization level when the analog voltage is 3.2 volts. d- The binary code produced by the ADC. e- The quatization error when the analog voltage is 3.2 volts.A reset input is used in IC 7493, why? a. For reset the counter b. For setting the counter c. For decrement of bit by 1 d. For increment of bit by 1A 9-bit asynchronous counter has a 128-kHz clock signal applied. (1) What is the MOD number of this counter? MOD number = (ii) What will be the frequency at the MSB output? fmsb = (iii) Assume that the counter starts at zero. What will be the count after 635 input pulses? After 635 input pulse, Count =
- Question 3 a) Convert the following unsigned binary numbers to decimal. i) 101101112 ii) 010011012 iii) 100101102 b) Assume a digital to analog conversion system uses a 10-bit integer to represent an analog temperature over a range of -100C to 1000C. If the actual temperature being read was 36.5oC, what would be the closest possible value that the system could represent? Expiain the term aliasing and discuss how it can be avoided in digital sampling. d) Show the output waveform of an AND gate with the inputs A, B, and C indicated in the figure below. A B C8085 microprocessor went through its manipulation operation in the ALU, the results was transferred on the data bus and status of the results was stored in the flag register for indications . With your knowledge and understanding illustrate a complete bit configuration of 8085 flag register and show the functions of the represented bits in the register.Write a Verilog code with testbench for 16-bit up/down counter with synchronous reset and synchronous up/down.If up/down is set the counter is up counter and if it is not set, the counter is a down counter. submit the module code, testbench code, and the simulation results. PLEASE EXECUTE CODE IN VERILOG