2.1. For W/L-50/0.5 and lo-500uA, compute the transconductance and output impedance of both NMOS and PMOS; Also find the intrinsic voltage gain 2.2. Derive expression for intrinsic transistor gain in terms of bias current lo and aspect ratio (W/L). If the channel length modulation is given by å= plot intrinsic gain vs drain current with channel length as parameter

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2.1. For W/L=50/0.5 and lo-500UA, compute the transconductance and output impedance of both
NMOS and PMOS; Also find the intrinsic voltage gain
2.2. Derive expression for intrinsic transistor gain in terms of bias current lo and aspect ratio (W/L). If the
channel length modulation is given by i plot intrinsic gain vs drain current with channel length
as parameter
Transcribed Image Text:2.1. For W/L=50/0.5 and lo-500UA, compute the transconductance and output impedance of both NMOS and PMOS; Also find the intrinsic voltage gain 2.2. Derive expression for intrinsic transistor gain in terms of bias current lo and aspect ratio (W/L). If the channel length modulation is given by i plot intrinsic gain vs drain current with channel length as parameter
Problem #3
Use the following process parameters
NMOS: Tx =9.10*m,H, = 350.10 [m² /V – S],V7, =0.7V,à=0.1V,y =0.45
PMOS: Tox =9.10*m,µ̟ =100.10 [m² /V – S],V7, =-0.8V,2=0.2V"',y = 0.4
Transcribed Image Text:Problem #3 Use the following process parameters NMOS: Tx =9.10*m,H, = 350.10 [m² /V – S],V7, =0.7V,à=0.1V,y =0.45 PMOS: Tox =9.10*m,µ̟ =100.10 [m² /V – S],V7, =-0.8V,2=0.2V"',y = 0.4
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