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- Excersize 2: Sketch a schematic of the circuit described by the following VHDL code. Simplify the schematic so that it shows a minimum number of gates. library IEEE; use IEEE.STD LOGIC 1164.all; entity exercise2 is port (a: in y: out STD_ LOGIC_VECTOR (1 downto 0)); STD LOGIC_VECTOR (3 downto 0); end; architecture synth of exercise2 is begin process (all) begin a (0) then y <= "11"; elsif a (1) then y <= "10"; elsif a (2) then y <= "01"; elsif a (3) then y <= "00"; y <= if else a (1 downto 0); end if; end process; end;Task: Modify the Laser Circuit FSM to output x for 25 ns, assuming Tclk = 5 ns. Given VHDL code for the Laser Circuit FSM: library ieee;use ieee.std_logic_1164.all; entity LaserTimer isport ( b: in std_logic;x : out std_logic;clk, rst : in std_logic;);end LaserTimer; architecture behavior of LaserTimer istype statetype is(S_Off, S_On1, S_On2, S_On3);signal currentState, nextState:statetype; beginstatereg: process(clk, rst)beginif (rst=’1’) thencurrentstate <= S_Off;elsif (clk=’1’ and clk’event) thencurrentstate <= nextstate;end if;end process; comblogic: process (currentstate, b)begincase currentstate iswhen S_Off =>x <= ‘0’;if (b=’0’) thennextstate <= S_Off;elsenextstate <= S_On1;end if;when S_On1 =>x <= ‘1’;nextstate <= S_On2;when S_On2 =>x <= ‘1’;nextstate <= S_On3;when S_On3 =>x <= ‘1’;nextstate <= S_Off;end case;end process;end behavior;Implement the following Boolean functions using (use only one De-mux for both functions) appropriate De-Mux and decoder. (use block diagram of De-Mux and decoder) F2(A,B,C,D) E(0, 1,3,9,13)
- Computer Engineering Subject name DLD . Code PS15 Task 3.1 Implementation of Combination Logic Circuit using PLA Like ROM, PLA can be mask-programmable or field-programmable. With a mask-programmable PLA, the user must submit a PLA program table to the manufacturer. This table is used by the vendor to produce a user-made PLA that has the required internal paths between inputs and outputs. A second type of PLA available is called a field-programmable logic array or FPLA. The FPLA can be programmed by the user by means of certain recommended procedures. FPLAs can be programmed with commercially available programmer units. ,As mentioned earlier, user has to submit PLA program table to the manufacturers to get the user-made PLA. Let the students to try how to determine PLA program table with the help of a question.Draw a PLA circuit to implement the logic functions A'BC + AB'C + AC' and A'B'C' + BC.• Draw block diagram showing the addition of 0110 and 1001 using Full Adders Implement a 5 to 32 decoder using - 2 to 4 decoders - 3 to 8 decoders - 4 to 16 decoders Implement the following function using 2 to 4 decoders -F(A, B, C, D) = m3 + m7 + m9 + m11 + m13 + m15 • Use a 4x1 multiplexer to implement the functions F(x, y, z) = Em(0, 1, 4, 5, 6) F(A, B, C, D) = Em(0, 2, 3, 7, 11, 13, 14) %3D %3DQ1: state whether the following identity is (a) POS,(b) SOP,) canonical POS,(d) canonical SOP: F(X,Y,Z)=XY'Z+X'Y'Z+X'Y'+XYZ
- Excersize 1: Sketch a schematic of the circuit described by the following VHDL code. Simplify the schematic so that it shows a minimum number of gates. library IEEE; use IEEE.STD_LOGIC_1164.all; entity exercisel is port (a, b, c: in Y, 2: STD LOGIC; out STD LOGIC); end; architecture synth of exercisel is begin y <= (a and b and c) or (a and not b and c); z <= (a and b) or (not a and not b); end; (a and b and not c) or6. Reduce the function specified in the truth table in figure below to its minimum SOP form by using K-map. A B 1 1 1 Ans: B+C 1 1 1 1 1 1 1 1 1 1 1 1 13. Use the Karnaugh-Map to simplify the following expressions F(A, B, C) = ABC + ABC + ABC + ABC + ABC F(A,B,C,D) = A + AB + ABC + BCD + ACD ii.
- 3. A Moore FSM outputs a '0' if an even number of l's have been received on the serial input line and the outputs a '1' otherwise. The entity declaration is given in the following for your convenience. entity odd_even_fsm is port (x. reset :in bit; : out bit); y end odd_even_fsm; a) Draw the state diagram of your design. b) Write VHDL code for the above Moore machine.Q2 Implement the function F(x1, x2, x3, x4) = II M(0,1,2,3,8,9,12,13) using 2 input look-up tables ( LUT- shown in figure 2 below ). Give the truth table implemented in each LUT. You do not need to show the wires in the FPGA, you need to show how the LUTS are connected . input 1 0/1 0/1 output 0/1 0/1 input 2 Fig 2 Circuit for a two-input LUTConsider the full adder shown in the figure bellow. Select the right choices from the drop-list of the code top-level design in VHDL in order to have 8- bit full adder entity N-bit-FA is generic (data_size: integer := 7); port (A, B in STD_LOGIC_VECTOR( < Sum in STD_LOGIC_VECTOR( + Cin, Cout: out STD_LOGIC); end N-bit-FA; architecture arch of shreg is COMPONENT FA IS PORT (A, B, Cin: IN STD_LOGIC; Co, S: OUT STD_LOGIC); END COMPONENT;