The three values the sequence counter (SC) cycle through the FETCH portion of the RSC instruction cycle are: __________________.
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- A(n) ____________________ instruction copies data from one memory location to another.A(n) ________________ instruction always alters the instruction execution sequence. A(n) ______________ instruction alters the instruction execution sequence only if a specified Condition is true.When an instruction is first fetched from memory, its placed in the _________________ and then ________________to extract its components.
- The time it takes to perform the fetch instruction and decode instruction steps is called the execution time. True or false?In the Allen-Bradley MOV instruction, constants such as 250, 400, 5.5, etc., can be entered into the source location of the MOV instruction rather than a memory address containing the value to be moved. True FalseQ:Non-Volatile Memory includes PROM (Programmable ROM) ROM (Read only Memory) EPROM (Erasable PROM) EEPROM (Electrically Erasable PROM) O RAM(Random access memory) Q: what is the addressing mode for the following instruction: LOAD (ABOO), Ri. * Register Mode Register Addressing Mode Immediate Mode Indexed Addressing Mode indirect mode direct mode
- The table shows the delays (pico second) of the components in Figure 4.17. Read/write PC I-mem D-mem Register file Mux ALU Adder And, Shifter Sign extend Control 10 250 150 25 200 150 10 50 50 Calculate the delay of the 4 types of instructions. You need to show which components are used in each instruction. Instructions: instruction delay time sd add beq ldGeneral purpose register EAX contains internal code (hexadecimal): 00020FFF General purpose register EDX contains internal code (hexadecimal): 01FF0C2B What is a decimal value of the register AL after execution of the following code? mov dl, ah add al, dl(d) The table below shows the ALUcontrol signal of the datapath we discussed in class. Instruction Funct ALU Орсode ALUop ALU action operation field control Iw 00 load word XXXXXX add 0010 Sw 00 store word XXXXXX add 0010 beq 01 branch equal subtract 0110 XXXXXX R-type 10 add 100000 add 0010 R-type 10 subtract 100010 subtract 0110 R-type 10 AND 100100 AND 0000 R-type 10 OR 100101 OR 0001 R-type 10 set on less than 101010 set on less than 0111 You want to add the bne instruction into the datapath, which already includes the required hardware for the instruction. Write out the ALUop for bne and how you can determine whether the bne results in the branch to be taken.
- PCSrc ID/EX EX/MEM Control IF/ID Add Branch MEM/WB Add Shift left 2 RegWrite Instruction Memory Read Address Read Addr 1 Register Read Read Addr Data 1 File Write Addr Data Memory MemtoReg ALUSrc Address Read Data ALU Read Data 2 Write Data Write Data ALU cntrl MemRead Sign Extend 16 32 ALUOP RegDst Figure 3: For EACH of the following registers, indicate how many bits are in the reg- ister, and what control signals are are in the register. he control signals in the diagram are: regWrite, regDest, aluOP, ALUsrc, Branch, MemRead, MemWrite, MemToReg. Register Number of bits Control Signals PC 32 None IF/ID 64* None ID/EX EX/MEM МЕM/WBThe instruction is stored at location 300 with its address field at location 301. The address field has a value of 400. A processor register R1 contains the number 200. Evaluate the effective address if the addressing mode of the instruction is Relative Addressing mode; • Relative: 300 + 200 = 500 • Relative: 302 + 200 = 502 • Relative: 301 + 400 = 701 • Relative: 302 + 400 = 702For the RISC-V assembly instructions below, what is the corresponding C statement? Assume that the variables f, g, h, i, and j are assigned to registers x5, x6, x7, x28, and x29, respectively. Assume that the base address of the arrays A and B are in registers x10 and x11, respectively: sub x30, x28, x29 slli x30, x30, 2 add x3, x30, x10 add x4, x30, x11 lw x30, 0 (x3) 1w x31, 0 (x4) add x30, x30, x31 sw x30, 16 (x11)