1. Function (subroutine) implementation requires Control instructions. (T/F) 2. We have one register file in LC-3 and all the instructions in all subroutines read and write from that one register file. 3. We use regular load and store instructions to access the status and data registers of a Memory Mapped IO (MMIO) device. 4. We use a handshaking protocol to control the exchange of data between a microcontroller and an asynchronous I/O device. 5. In a system with an OS, a programmer can directly access I/O registers.

1. Function (subroutine) implementation requires Control instructions. (T/F) 2. We have one register file in LC-3 and all the instructions in all subroutines read and write from that one register file. 3. We use regular load and store instructions to access the status and data registers of a Memory Mapped IO (MMIO) device. 4. We use a handshaking protocol to control the exchange of data between a microcontroller and an asynchronous I/O device. 5. In a system with an OS, a programmer can directly access I/O registers.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter11: Operating Systems

Section: Chapter Questions

Problem 30VE

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[Direction: You can consult any resources such as books, online references, and videos for this assignment, however, you have to properly cite and paraphrase your answers when it is necessary.] The following figure represents both datapath and controlpath for MIPS architecture that implements most of the fundamental instrucons.
Question 4: There is an application that requires the hardware: an Intel 8031, a Program ROM of 8Kx8, a Data ROM of 4Kx8 for look-up tables, TWO Data RAMs of 8Kx8. The memory map of the design should be: Program ROM should start at address 0000μ. Then, the Data ROM should come above the Program ROM. Finally the Data RAMs must go to the top of the memory map. There should be no gaps between the memory addresses of the external ROMs or RAMS. A. Using logic gates, draw the pin connections of the design. Label your diagram fully. B. Calculate the address space of the ROMs and RAMs of your design. C. Show the design's address space on a memory map, starting with 0000μ at the bottom and FFFFH at the top.
2. There are interrupt in 8086 Mp, user, starting from interrupt number_ of them are available for the 3. IVT is a table that contain the of ISR of each interrupt. The size of the table is 4. The low bank (even bank) in 8086Mp memory has a size of bytes, starting from address: and ending with address:_
True/False During the 'READ' of the SRAM structure studied in the class, the bit and bit_bar are both precharged to a high, and then the word line is turned high. This will always result in one of the bit or the bit_bar lines to start tending to go low, while the other remains at the precharged levels.
Assume that an interrupt mechanism uses the hardware stack to store PC and other registers of the interrupted computations. The interrupt mechanism recognizes 4 interrupt vectors IV [1], IV [2], IV [3], IV [4] initialized by addresses of their corresponding ISR I =1..4. The elements of the hardware stack are a record R, where each field stores a specific CPU register (R.PC is the field, which stores the program counter PC and so on). The Hardware stack is manipulated using the standard stack operation Pop, Push, EmptyStack.a) Explain how the CPU detects an interrupt signal I and what actions should be taken?b) Write the initial and final sequences of instruction of a given ISR I (Transparency).c) Write the ISR4 such that whatever number of interrupted computation (in the stack) it gives the control to the first one interrupted.
Carefully read each sentence in this question. You may agree/disagree with each sentence (consider each sentence separately) if you have a good justification for doing so (not in more than 2 lines for each sentence). “A daisy chaining technique could result in starvation.” “The received data is saved in contiguous memory regions in DMA transfer.” “The most difficult method of device identification is multiple interrupt lines.” “An interrupt request takes longer for the CPU to handle than a DMA request.” “The architecture of InfiniBand operation is layered.”
LDR uses an address called a "Register Offset" address. Why? Group of answer choices The data value loaded is at an address in the memory. The data value loaded is the results of adding a register and immediate to obtain the reference for the data value Memory is accessed at a location that is a numeric value, starting at (offset from) 0 The ALU can only use register (not memory) values All data access is relative to a memory address or 0. The LDR command uses what units in the CPU? Select all that apply. Group of answer choices Data Memory Multiplication Unit Barrel shifter ALU Addition is done in what CPU unit? Group of answer choices The multiplication unit The registers The ALU The barrel shifter
The control signal Ep or iEnableoutput allows the program counter to decrement its value. True False The control signal Ep or iEnableoutput sends the content of the program counter to the W bus. True False A tri-state buffer is needed for all data going to the W bus. True False In using 'assign' statement in Verilog, the left hand side must always be a register. True False In declaring a register in Verilog, the following format must be followed: reg [LSB:MSB] identifier; True False
Assume that an interrupt mechanism uses the hardware stack to store PC and other registers of the interrupted computations. The interrupt mechanism recognizes 4 interrupt vectors IV [1], IV [2], IV [3], IV [4] initialized by addresses of their corresponding ISRI=1.4. The elements of the hardware stack are a record R, where each field stores a specific CPU register (R.PC is the field, which stores the program counter PC and so on). The Hardware stack is manipulated using the standard stack operation Pop, Push, EmptyStack. a) Explain how the CPU detects an interrupt signal I and what actions should be taken ? b) Write the initial and final sequences of instruction of a given ISR I. (Transparency). c) Write the ISR4 such that whatever number of interrupted computation (in the stack) it gives the control to the first one interrupted.
Write a service routine which resets all elements of an array that resides in memory location from A000 H to A0FF H with DS equal to 0000 H. The service routine address is CS:IP where CS is 2000 H and IP is 0100H. Assume the interrupt type that is called is 50 (x8086- nano)
a. Find the address accessed by each of the following instructions. If DS = 0100H, BX= 0120H, DATA = 0140H, and SI = 0050H and real mode operation:1. MOV DATA[SI], ECX2. MOV BL, [ BX+SI]b. Descriptor contains a base address of 00260000H, a limit of 00110H, and G = 1,determine starting and ending locations are addressed by the descriptor for aCore2.
[ Direction: Any how solve the question please. Don't reject the question. if you need 2 /3 hours to solve the question please take it but don't reject the question. solve it properly,correctly.You can consult any resources such as books, online references, and videos for this assignment, however, you have to properly cite and paraphrase your answers when it is necessary. ] The following figure represents both datapath and controlpath for MIPS architecture that implements most of the fundamental instrucons.