Implement a circuit that receives 4-bit message and outputs Error (E=1) if its parity is ODD. (Implement it using XOR and XNOR gates)
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Implement a circuit that receives 4-bit message and outputs Error (E=1) if its parity is ODD.
(Implement it using XOR and XNOR gates)
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- Finite state machine (FSM) counter design: Design a finite state machine that detects the following sequence of serial inputs on input A: 0111. The output Y should assert every time that sequence of bits is encountered in the input stream. You may assume that input A becomes a new value (i.e., the next bit) shortly after each clock edge. Show all the steps of FSM design from the black box and state transition diagram all the way to the circuit (and all the steps in between).Hint: For example, the following series of values on A could occur. After each sequence of the desired pattern (0111) is detected (highlighted in orange or green -- see attached), output Y should assert. Start with SR state to S0111 state.Finite state machine (FSM) counter design: Design a finite state machine that detects the following sequence of serial inputs on input A: 0111. The output Y should assert every time that sequence of bits is encountered in the input stream. You may assume that input A becomes a new value (i.e., the next bit) shortly after each clock edge. Show all the steps of FSM design from the black box and state transition diagram all the way to the circuit (and all the steps in between). Hint: For example, the following series of values on A could occur. After each sequence of the desired pattern (0111) is detected (highlighted in orange or green -- see attached), output Y should assert. A: 0101001110010111011100101001000100111111010111011010111011111110111011101DFF circuit that adds the one-bit numbers a and b in series. Design according to the Mealy model a)state diagram b)state table c)simplification with Karnaugh maps
- Q1: Design and implement an asynchronous counter that counts from 0000 up to 1100 (modulus 13). Use OR gate, and show in the drawing how the OR gate is connected to truncate the state 1101.Question 1 Design the following circuits by using only 2x1 MUXs and NOT gates. 4X1 MUX 8X1 MUX 2-inputs AND GATE 2-inputs OR GATE Question 2 Design a JKFF by using only a DFF and logic gates. Question 3 Design a sequential modulo 3 accumulators for 2-bit operands. Definition:Accumulator - a circuit that “accumulates” the sum of its input operands over time - it adds each input operand to the stored sum, which is initially 0.Consider the following runtime stack: BEFORE 00001000 00000006 ESP 00000FFC 00000FF 8 00000FF 4 00000FF0 What would be the value of ESP after pushing the 32-bit value shown below onto the stack? 000000A5 O 00001020 O 00000FF8 O 00000FFC O 000000A5
- A seven-segment display is a device composed of 7 elements, as shown in the figure below. Each element is selectively lit to form patterns such as numbers or letters. For example, to display '0', the segments A, B, C, D, E and F have to be simultaneously lit. A circuit decoder takes in a 4-bit binary number and produces the outputs A, B, C, D, E, F and G. The outputs of the decoder are then fed to the seven-segment display as shown in the figure. The seven-segment display should show the sum of the 4-bit input + 1. For example, if the 4-bit input is 000 , the decoder’s output will lit up the seven-segment display that will show the numerical number 1. This corresponds to the decoder output of 01100002. In the case wherein the 4-bit input = 1001 , the decoder’s output will lit up the seven-segment display that will show the numerical number 0. This corresponds to the decoder output of 1111110 . The decoder’s output line should be logic “1” if the segment will be lit and “0” otherwise.…Question 1 Design the following circuits by using only 2x1 MUXs and NOT gates. 2-inputs OR GATE Question 2 Design a JKFF by using only a DFF and logic gates. Question 3 Design a sequential modulo 3 accumulators for 2-bit operands. Definition:Accumulator - a circuit that “accumulates” the sum of its input operands over time - it adds each input operand to the stored sum, which is initially 0.Excess-3 code is significant for arithmetic operations as it overcomes shortcoming encountered while using 8421 BCD code to add two decimal digits whose sum exceeds 9. Excess-3 arithmetic uses different algorithm than normal non-biased BCD or binary positional number system. An electronics company has hired your services to design a code converter that converts Binary Coded Decimal (BCD) code for it. Design the converter.
- Q1. a) If 8-bit numbers are used, the two's complement decimal representation covers the range from (most positive). (most negative) to b) Show how to build a 2-input NOR gate from 2-to-1 MUXes. You can freely connect inputs to "1" and "0" as needed. Label the inputs as "A" and "B". Label the output as "X". Your solution must use 3 or fewer 2-to-1 MUXes to receive credit. c) Design an active low D latch with enable input C using only NOR gates and inverters. (Active low D-latch: enabled when enable signal low. Disabled when enable signal high.)Binary codes.Convert from Gray code to binary X1 = 10101111. From the result obtained, apply a complement to 2. Also, comment on an application of this code in particular.A 14-bit ADC with VFS = 5.12 V has an output code of 10101110110010. What is the possible range of input voltages?